Optimizing Neural Network Performance by Integrating ASICs Optimized for Machine Learning with SDRAM

Abstract

With steady advances in neural network technology, it has become necessary to develop hardware that is better suited to running neural networks. Many different hardware systems have been developed for this purpose, but here we focus on an Application Specific Integrated Circuit (ASIC) developed by Professor Naveen Verma’s group at Princeton University. This chip has demonstrated superior efficiency and power usage when compared with other similarly intentioned topologies. However, it lacks sufficient memory capacity to easily run the more complicated neural networks that are currently being developed. In this work, I propose adding a Synchronous Dynamic Random Access Memory (SDRAM) component to the existing ASIC in order to resolve this issue. I hope that this addition will allow this chip to run more complicated neural networks with larger training datasets more efficiently.