Device-circuit co-design approaches for Multi-gate FET technologies

Abstract

Planar CMOS technology has reached its scaling limits at the 22nm node, where it is increasingly difficult to design high-performance low-power devices with good yield in the presence of global and local process variations. Multi-gate FET technology is the best alterative that can extend scaling to the sub-10nm technology nodes

with minimum additional processing costs. However, owing to the non-planar nature of multi-gate devices, several challenges in process technology, CAD/layout design, and testing need to be addressed to enable design portability from planar

to multi-gate FET chips.

This thesis strives to bridge the device-circuit co-design gap that has severely limited predictive modeling of circuits using emerging multi-gate/FinFET devices during early stages of process technology development. First, the traditional notion of leveraging independent-gate devices for power reduction is challenged, by contrasting logic gates having symmetric gate-workfunction shorted/independent-gate FinFETs alongside logic gates having asymmetric gate-workfunction shorted-gate FinFETs, in a high-performance process. The superiority of asymmetric gate-workfunction devices is demonstrated by comparing leakage-delay trends, and the downsides of logic gates employing a mix of shorted and independent-gate devices is brought out from a testing/fault modeling perspective.

Next, efficient methodologies are developed for unifying the layout and process simulation worlds, in order to breach the `many-device TCAD barrier' that has limited the applicability of 3D-TCAD modeling for over a decade. Here, important bottlenecks for layout to 3D circuit structure generation, such as the time and memory complexity of 3D process simulation, are identified. To bypass the latter, a radically new layout-/process-/device-independent approach based on

automated structure synthesis is proposed and evaluated for accuracy and scalability, using SRAM bitcell structures with 32/22nm process assumptions.

After addressing the 3D-TCAD structure generation issue, several hitherto intractable problems, such as true 3D parasitic capacitance extraction for generic multi-gate circuit layouts in sub-32nm technology nodes, entered the realm of possibility. Here, the need for transport analysis based capacitance extraction is explained, by highlighting the difference between field solver based extractions and TCAD based extractions on sub-32nm IBM SOI SRAMs. Thereafter, the combination of structure synthesis and transport analysis based extraction is validated with hardware data from two companion 6T SRAM arrays fabricated in an IBM 32nm SOI HKMG process. Next, a multi-gate version of the structure synthesizer is used to predict and analyze key parasitic capacitance trends in 6T multi-gate SRAMs at the 22/14/10nm technology nodes.

Finally, this thesis delineates a path to enable multi-gate layout/process/circuit co-design, using a unified 3D/mixed-mode 2D-TCAD methodology for systematically designing and evaluating different 6T FinFET SRAM bitcell topologies in a 22nm SOI process. Here, the role of parasitic capacitances, i.e., their dependencies on fin/gate pitch, etc., are examined in detail, and the need to evaluate multi-gate bitcells based on dynamic behavior, rather than DC metric targets, is highlighted.