Development and Characterization of Low-Disorder Metal-Oxide-Silicon Quantum Dot Devices

Abstract

Spins confined in Metal-Oxide-Silicon (MOS) quantum dot devices are promising qubits in a quantum processor, demonstrating long coherence times, a large valley splitting, and coherent interactions with donor qubits. Furthermore, the mature fabrication infrastructure of the CMOS industry offers a tantalizing roadmap towards scaling to extremely large quantum systems on a single silicon chip. Despite the incredible advances in materials and fabrication developed by the classical CMOS industry and continued by the silicon quantum electronics community, many challenges remain in building a silicon quantum processor. One of the biggest challenges impeding the scaling of large quantum dot systems is the presence of disorder and shallow electron traps at the Si/SiO2 interface. The purpose of this thesis is to illuminate mechanisms of disorder at the Si/SiO2 interface relevant to quantum dot devices, develop a framework for understanding and quantifying shallow electron traps in terms of electron spin resonance and transport measurements, and to pave a path forward for scaling MOS quantum dot devices.

This thesis is organized into three sections: first, we develop a fabrication process in silicon MOSFETs yielding a low-disorder Si/SiO2 interface in order to leverage this process as a platform for fabricating low-disorder quantum dot devices. One of the challenges in working with silicon oxide is that high energy processes and mobile ionic contamination during the fabrication process can create electron traps and disorder at the Si/SiO2 interface. Using the low temperature (4.2 K) electron mobility as a proxy for the Si/SiO2 interface quality, we study the effect of various processing parameters on the Si/SiO2 interface disorder and ultimately arrive at a fully optimized process yielding the highest reported mobility (23,000 cm^2/Vs) thin-oxide (less than or equal to 30 nm) silicon MOSFET.

Secondly, we study the annealing of shallow electron traps created by electron-beam (e-beam) lithography. E-beam lithography is a necessary tool in defining nano-scale electrostatic gates which define the quantum dot potential, but the high-energy electrons and photons created in the process create electron traps at the interface. We directly probe shallow electron traps using electron spin resonance (ESR) and demonstrate that 1) a standard forming gas anneal is sufficient to passivate electron traps created by the e-beam exposure, and 2) that our lowest temperature ESR measurements agree with transport measurements of the devices' percolation threshold, demonstrating agreement between two independent methods of characterizing the Si/SiO2 interface.

Finally, leveraging the above process optimizations, we fabricate and characterize a low-disorder double quantum dot device. We demonstrate agreement between the dots' charging energy and lithographic size, concluding that our dots are lithographically defined and not dominated by random disorder. Charge sensing measurements indicate regular quantum dot transitions over a wide parameter range down to the single electron regime, with evidence of few defects in the vicinity of the quantum dots, and the controllable formation of a quantum double dot. Noise spectroscopy measurements of the dot indicate a 1/f like power spectral density that is comparable in magnitude to other Si quantum dot devices measured at 300 mK. Finally, magneto-spectroscopy measurements of the first and second electron transitions yield a valley splitting of 110+/-26 ueV, large enough to support high-fidelity spin selective operations.

With this work, we demonstrate a method of fabricating low-disorder, high-mobility silicon MOSFETs, a framework for studying disorder in quantum dot devices in the low-electron density regime, and a promising platform for MOS qubits in a low-disorder quantum dot device architecture.