Design of Dynamically-Reconfigurable Architectures Aimed at Reducing FPGA-ASIC Gaps

Abstract

Field-programmable gate arrays (FPGAs) have become an attractive alternative to application-specific integrated circuits (ASICs) due to shorter time-to-market and lower design cost. On the other hand, the hardware programmability provided by FPGAs introduces design overhead, which results in 21X more area, 3X longer delay, and 10X more dynamic power consumption compared to ASICs.

This thesis focuses on architecture designs and optimization techniques that aim at bridging the FPGA-ASIC gaps. The explorations are based on an advanced FPGA reconfiguration model, called temporal logic folding, which partitions applications into a sequence of stages to temporally share the same hardware resources. First, the concept of logic folding is applied to a CMOS-based conventional FPGA architecture augmented with distributed 10T-SRAM blocks, called SRAM-based NATURE. The distributed high-performance low-power memory blocks in SRAM-based NATURE enable cycle-by-cycle run-time reconfiguration without a large power overhead. The area usage is significantly reduced, which also improves the interconnect performance and power consumption.

Next, observing that logic folding reduces area significantly and most of interconnects are localized, the thesis proposes a new fine-grain dynamically reconfigurable architecture (FDR) that is specifically optimized for logic folding. FDR consists of an array of homogeneous logic elements (LEs) that can be configured into logic, interconnect, or both. It eliminates most of the global interconnect resources, which occupy a large fraction of area in conventional FPGAs. The thesis also presents the corresponding automated design flow, called FDRMap, which maps applications onto FDR. It discusses various optimization techniques exploited in FDRMap. It then presents an extension of FDR that incorporates coarse-grain blocks, including digital signal processing (DSP) blocks and data memories, in its augmented version, called FDR 2.0, to further improve performance and design flexibility. It is implemented using low-power FinFET circuit design techniques to lower power consumption without degrading circuit performance. Experiments show that FDR and FDR 2.0 can achieve more than an order of magnitude improvement in the area-delay product with smaller power consumption compared to conventional FPGAs that do not use logic folding. Although the current FPGA-ASIC area/delay/power gaps are not fully eliminated, this makes progress toward bridging these gaps.